Charge pump systems and methods

ABSTRACT

A charge pump circuit includes capacitors and a number of forcing circuits for forcing the voltages on various nodes of the charge pump. The forcing circuits ensure that voltage differences across components thereof are up-limited in absolute value by a predetermined maximum voltage equal to a multiple of the absolute value of the difference between developed forcing voltages and lower than an absolute value of a charge pump voltage. The first and second forcing circuits ensure that the voltage differences across components in the forcing circuits are not higher than the predetermined maximum voltage when at least one among the voltages changes to a voltage higher in absolute value than said predetermined maximum voltage.

This application claims priority from European patent application Nos.EP05111284.5, filed Nov. 25, 2005, EP06111337.9 filed on Mar. 17, 2006,EP06111477.3 filed on Mar. 21, 2006, EP06112526.6 filed Apr. 12, 2006,EP06113480.5 filed May 4, 2006, EP06119456.9 filed Aug. 24, 2006 andEP06119440.3 filed Aug. 24, 2006 all of which have a common assignee andwhich are incorporated by reference.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. ______,entitled “Non-volatile memory implemented with low-voltages transistorsand related system and method” (Attorney Docket No. 2110-225-03), whichhas a common filing date and assignee and which is incorporated byreference.

TECHNICAL FIELD

An embodiment of the present invention relates to the field of thesemiconductor Integrated Circuits (ICs), and more particularly, itrelates to ICs that have to manage differentiated voltage levels.

BACKGROUND

ICs can be classified in two broad categories, depending on the voltagedifferences that occur across the terminals of the electronic devicesincluded therein.

More specifically, in ICs belonging to a first category, called from nowon “low voltage ICs”, all the electronic devices included therein (e.g.,the transistors and the capacitors) are designed in such a way toguarantee the capability of sustaining, between their terminals, voltagedifferences that are up-limited (in absolute value) by a predeterminedmaximum voltage difference ΔVml, e.g. equal to an IC supply voltagevalue Vdd. The voltage differences experienced by the devices includedin the low voltage ICs are such as to allow the correct functioning ofstandard devices (like those making up the logic circuitry included inICs) without causing malfunctioning or breaking thereof, that may becaused instead by excessive voltage differences. Referring for exampleto ICs including transistors like BJTs or FETs, particularly IGFETs, thepredetermined maximum voltage difference ΔVml may be equal to the supplyvoltage Vdd, in such a way to avoid the occurrence of gate insulators(oxides) breaking down, or unwanted junction breakdowns. In particular,as far as Metal Oxide Semiconductor (MOS) transistors, Low Voltage (LV)MOS transistors (hereinafter, LV transistors) are devices adapted toguarantee the capability of sustaining between their terminals voltagedifferences that are up-limited by the IC supply voltages Vdd.

The low voltage IC is designed in such a way that, in operation,practically all the transistors included therein experience voltagedifferences equal to the supply voltage Vdd or less, at least betweentheir control terminal, e.g., the gate terminal, and any other terminalthereof (avoiding thereby the occurrence of gate insulators breakingdown), and preferably between pair of terminals corresponding tosemiconductor junctions (avoiding thereby the occurrence of junctionbreakdowns).

The ICs belonging to the second category, termed hereinafter called fromnow on “high voltage ICs”, include instead, in addition to low-voltagedevices, devices designed in such a way to guarantee the capability ofsustaining, at least between a pair of their terminals, voltagedifferences up-limited by a predetermined maximum voltage differenceΔVmh higher than the predetermined maximum voltage difference ΔVml thatthe devices included in low voltage ICs are guaranteed to withstand.Referring again to the example of circuits including transistors, thehigh voltage circuits include one or more transistors biased in such away to experience voltage differences at least between their gateterminal and any other terminal thereof that are higher than the ICsupply voltage Vdd.

ICs of such category are for example common in the field of memorycircuits. In particular, in non-volatile memories high voltages areneeded to modify the stored data (e.g., to program and/or erase thememory cells of the memory, in such a way to activate known physicalphenomena such as Channel Hot Electron (CHE) and Fowler-NordheimTunneling (FNT). The transistors used in such high voltage ICs need tobe capable of withstanding high voltage differences across theirterminals, without damaging or malfunctioning, for example not totrigger CHE or FNT. In fact, while for a memory cell the CHE and FNTeffects are desired and controlled for the purposes of modifying thestored data, said effects are in turn deleterious for the transistors ofthe rest of the IC, like the logic circuitry.

As another example, in volatile memories, such as in SRAMS and DRAMS,high voltages higher than the IC supply voltage Vdd can be used forbiasing the cells of the memory, in such a way to improve the speed ofthe reading operations.

In the case of high voltage ICs comprising MOS transistors, High Voltage(HV) MOS transistors (hereinafter, HV transistors) need to be designedand integrated, which are adapted to guarantee the capability ofsustaining, at least between a pair of their terminals, voltagedifferences up-limited by the predetermined maximum voltage differenceΔVmh, higher than the IC supply voltage Vdd. In particular, HVtransistors may have a gate oxide layer thicker than that normally usedfor the standard, Low Voltage (LV) transistors, i.e., the MOStransistors typically used in low voltage ICs. HV transistors thus havea higher threshold voltage value, and the use of a thicker gate oxideavoids occurrences of oxide breaking, even with relatively high voltagedifferences applied between gate and channel.

However, the necessity of using HV transistors poses constraints to thetechnology used to fabricate the IC. More particularly, even if thescaling of the transistors size, made possible by the evolution of themanufacturing technologies, allows one to drastically reduce thedimensions of the LV transistors, the gate oxide thickness of the HVtransistors can not be thinned. Consequently, it is not possible toshrink the dimensions of the HV transistors, and thus it is hard toachieve the desired reduction in the silicon area occupied by the ICsincluding high voltage circuits.

One of the methods that is more commonly adopted, is to design highvoltage circuits using both LV and HV transistors. More particularly,since the HV transistors occupy more silicon area compared to the LVtransistors, it is possible to save silicon area using HV transistorsonly where they are strictly necessary. However, this method has a majordrawback, given by the fact that the manufacturing process has toinclude a higher number of processing steps and masks, for example fordifferentiating the oxide thickness and the threshold voltages of the HVand LV transistors.

The relatively high voltages needed by an IC may be provided from theoutside of the IC, or, more advantageously, in so-called Single PowerSupply (SPS) ICs, they are generated directly on chip. In the lattercase, the generation of the high voltages is accomplished by dedicatedboosting circuits, like charge pumps, capable of generating voltageshigher than the IC supply voltage, starting from the latter. It has tobe noted that the term “voltages higher than the supply voltage”, has tobe intended both as “voltages higher than the positive supply voltage”(namely, Vdd), and voltages lower than the most negative supply voltage”(i.e., the ground voltage GND or a negative supply volt Vss).

In particular, positive charge pumps are adapted to generate positivevoltages higher than the starting IC supply voltage, whereas negativecharge pumps are adapted to generate negative voltages, starting fromthe IC supply voltage.

Known types of charge pumps are the so called “parallel charge pumps”and “serial charge pumps”. Both comprise a plurality ofcascade-connected stages, each one including a capacitor. The differenceessentially consists in the fact that while in a parallel charge pumpthere is a phase in which the capacitors are arranged in parallel, in aserial charge pump there is a phase in which the capacitors areconnected in series. Both parallel and serial charge pumps, in knowncircuit design, need the use of HV transistors.

SUMMARY

In view of the state of the art outlined in the foregoing, the problemof how to improve the known solution for implementing charge pumps hasbeen studied. Particularly, the problem of how to realize a charge pumpthat does not make use of HV transistors has been studied.

It has been found that, by adopting a serial charge pump architecture,it is possible to avoid using HV MOS transistors.

According to an embodiment of the present invention, a charge pumpcircuit comprises at least one pump stage. Said pump stage includes acapacitor having a first plate and a second plate. The pump stagefurther includes a first circuital node connected to the first plate, avoltage of the first circuital node is forced to a first forced voltageduring a forcing phase of the charge pump operation, and a secondcircuital node connected to the second plate, a voltage of the secondcircuital node is forced to a second forced voltage during the forcingphase. The voltages of the first and the second circuital nodes are freeof changing with respect to the first and to the second forced voltage,respectively, except during said forcing phase. The pump stage stillfurther includes a first forcing circuit associated with the firstcircuital node, the first forcing circuit being activable for forcingthe voltage of the first circuital node to the first forced voltageduring the forcing phase, and a second forcing circuit associated withthe second circuital node, the second forcing circuit being activatablefor forcing the voltage of the second circuital node to the secondforced voltage during the forcing phase. The first and second forcingcircuits comprise each at least one electronic device having terminals.Said at least one electronic device is designed to guarantee thecapability of sustaining voltage differences across the terminalsthereof that are up-limited in absolute value by a predetermined maximumvoltage equal to a multiple of the absolute value of the differencebetween the first and the second forcing voltages and lower than anabsolute value of a charge pump voltage. The first and second forcingcircuits include means for ensuring that the voltage difference appliedacross pair of terminals of said at least one electronic device is nothigher than the predetermined maximum voltage when at least one amongthe voltages of the first and the second circuital nodes change to avoltage higher in absolute value than said predetermined maximumvoltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are set forth in the appendedclaims. Further features and advantages of various embodiments of thepresent invention will be best understood by reference to the followingdetailed description, given purely by way of a non-restrictiveindication, to be read in conjunction with the accompanying drawings:

FIG. 1 illustrates a schematic view of a positive serial charge pumpaccording to a first embodiment of the present invention;

FIGS. 2A, 2B and 2C illustrate the voltage values of a plurality ofcircuital nodes of the charge pump of FIG. 1 during three operatingphases thereof;

FIGS. 3A-3F illustrates the circuital structure of forcing circuitsconnected to the nodes of the charge pump of FIG. 1;

FIG. 3G shows the circuital structure of a voltage regulator included inthe pump, according to a second embodiment of the invention;

FIG. 3H shows the circuital structure of a voltage regulator included inthe pump, according to a third embodiment of the invention;

FIG. 4 illustrates a schematic view of a negative serial charge pumpaccording to a fourth embodiment of the present invention;

FIGS. 5A, 5B and 5C illustrate the voltage values of a plurality ofcircuital nodes of the charge pump of FIG. 4 during three operatingphases thereof; and

FIGS. 6A-6F illustrates the circuital structure of forcing circuitsconnected to the nodes of the charge pump of FIG. 4.

In the following, two types of serial charge pumps according to possibleembodiments of the present invention will be described, namely apositive charge pump and a negative charge pump.

DETAILED DESCRIPTION

The following discussion is presented to enable a person skilled in theart to make and use the invention. Various modifications to theembodiments will be readily apparent to those skilled in the art, andthe generic principles herein may be applied to other embodiments andapplications without departing from the spirit and scope of the presentinvention. Thus, the present invention is not intended to be limited tothe embodiments shown, but is to be accorded the widest scope consistentwith the principles and features disclosed herein.

Positive Charge Pump

Referring in particular to FIG. 1, a positive serial charge pump 100according to an embodiment of the present invention is schematicallyillustrated. The purpose of the charge pump 100 is to generate positivevoltages higher than the IC supply voltage, starting from the latter.More particularly, the charge pump 100 includes a cascade of stages, inthe example herein considered three stages. For example, the charge pump100 is integrated in an IC, such as a semiconductor memory IC, and isadapted to generate a relatively high voltage used to program/erasememory cells. It has to be noted that the charge pump herein describedis an exemplary one, in the sense that the number of stages (and thusthe number of capacitors) is merely indicative. Indeed, otherembodiments of the present invention may be applied to a positive chargepump having a different number of capacitors (and thus, having differentvoltage values at the output node).

The generic stage includes a capacitor, like the three capacitors C1,C2, C3. The three capacitors are series connected by means of twoswitches S1, S2.

The charge pump also includes a plurality of forcing circuits 110, 120,130, 140, 150, 160 adapted to force voltages on a plurality of nodes N1,N2, N3, N4, N5, N6 of the charge pump in such a way to properly chargethe capacitors C1, C2 and C3, and a logic block 170, adapted to generatecontrol signals whose purpose will be explained in the following of thedescription.

More particularly, the capacitor C1 includes a first plate (incorrespondence of the node N1) connected to an output terminal of theforcing circuit 110, and a second plate (in correspondence of the nodeN2) that is connected to a first terminal of the switch S1. Moreover,the node N1 is further connected to an input terminal of the forcingcircuit 130, and the node N2 is further connected to an output terminalof the forcing circuit 120.

The switch S1 includes a P-channel MOS (hereinafter, PMOS) transistorshaving a first and a second terminals (the drain/source terminals), acontrol terminal (the gate terminal) and a bulk terminal. Since MOStransistors are semiconductor devices having a symmetric structure, withthe drain and source terminals that are interchangeable, for the sake ofsimplicity, in this description drain and source terminals will be notclearly distinguished, and reference will be made only to generic“first” and “second” terminals. The gate terminal of the PMOS transistorof the switch S1, i.e. the switch control terminal, is connected to afirst output terminal of the logic block 170 (node L1), the bulkterminal is connected to the node N2, and the second terminal, formingthe second terminal of the switch S1, is connected to the first plate ofthe capacitor C2 (in correspondence of the node N3). Moreover, the nodeN3 is connected to an output terminal of the forcing circuit 130.

The capacitor C2 has a second plate connected to a first terminal of theswitch S2 (in correspondence of the node N4). The node N4 is furtherconnected to an output node of the forcing circuit 140.

The switch S2 includes a P-channel MOS transistor having a controlterminal (the gate terminal) connected to the node N2, a bulk terminalconnected to the node N4, a first terminal forming the first terminal ofthe switch, and a second terminal, forming a second terminal of theswitch S2, connected to a first plate of the capacitor C3 (incorrespondence of the node N5). Moreover, the node N5 is furtherconnected to an output terminal of the forcing circuit 150.

The capacitor C3 has a second plate connected to an output terminal ofthe forcing circuit 160, in correspondence of the node N6. The node N6,forming the output node of the charge pump, is further connected to aload, schematized as a bipole L. For example, the load may be a part ofthe IC wherein the charge pump is integrated that needs to use therelatively high voltage generated by the charge pump.

The logic block 170 further includes a second output terminal connectedto input terminals of the forcing circuits 120, 130, 140, 150 and 160(node L2), and a third output terminal connected to an input terminal ofthe forcing circuit 110 (node L3).

The forcing circuits 130 and 140 have a respective further inputterminal connected to the node N2; the forcing circuit 150 has threefurther input terminals connected to the nodes N4, N2 and N3respectively; the forcing circuit 160 has two further input terminalsconnected to the node N2 and N4 respectively.

To better explain the operation of the charge pump 100, reference willbe made now to the FIGS. 2A, 2B and 2C, illustrating simplifiedequivalent circuits of the charge pump 100 during three differentoperating phases: a precharging phase (FIG. 2A), a charge sharing phase(FIG. 2B), and a voltage boosting phase (FIG. 2C). More particularly, inthe charge pump operation, these three phases are repeatedly performed.

The first, precharging phase serves to charge each one of the capacitorsC1, C2 and C3 to the supply voltage Vdd of the IC (in this example equalto 3 Volts). In particular, during this phase, the switches S1 and S2are open, and each capacitor C1, C2 and C3 is thus isolated from theother two. The forcing circuits act on the corresponding nodes, so as tobias the first plates of the capacitors to voltages equal to the groundvoltage GND, and to bias the second plates of the capacitors to thesupply voltage Vdd. Consequently, the forcing circuit 110 biases thenode N1 to the ground voltage GND; the forcing circuit 120 biases thenode N2 to the supply voltage Vdd, in the example of 3 Volts; theforcing circuit 130 biases the node N3 to the ground voltage GND; theforcing circuit 140 biases the node N4 to a voltage of 3 Volts; theforcing circuit 150 biases the node N5 to the ground voltage GND; andthe forcing circuit 160 biases the node N6 to a voltage of 3 Volts.

After the precharging phase, each capacitor C1, C2, C3 stores anelectrical charge that depends on the respective capacitance value, andon the voltage difference applied across its plates. For example,assuming that all the capacitors C1, C2 and C3 have the same capacitancevalue, and since in the precharging phase a voltage difference equal tothe supply voltage Vdd is applied across the plates of each one of thecapacitors C1, C2, C3 thanks to the series connection of all thecapacitors guaranteed by the particular topology of the charge pump,each capacitor stores essentially an equal amount of electrical charge.

In the second, charge sharing operating phase, the switches S1 and S2are made to close, so as to connect in series the capacitors C1, C2, C3.Thanks to the series connection, the electrical charge previously storedin each capacitor C1, C2, C3 is shared with that stored in the adjacentcapacitor. Moreover, the forcing circuits associated with the nodes thatmodify their voltage values during this phase are disconnected from thecorresponding nodes, where, by “disconnected” there is intended a lackof a low-impedance path towards a terminal providing the supply voltageVdd or a terminal providing the ground voltage GND.

Consequently, the stored electrical charge is redistributed along theseries connection. This involves a change of the voltages at each nodeof the pump 100. More particularly, while the node N1 remains at theground voltage GND and the node N2 remains at 3 Volts, the voltage atnode N3 becomes equal to 3 Volts, the voltage at node N4 becomes equalto 6 Volts, the voltage at node N5 becomes equal to 6 Volts, and thevoltage at node N6 becomes equal to 9 Volts.

In the third, boosting phase. the switches S1 and S2 remain closed as inthe previous phase, and the forcing circuit 110 brings the node N1 fromthe ground voltage GND to a voltage of 3 volts. Since all the nodes areconnected by means of a capacitive serial connection, the voltage ateach node N2, N3, N4, N5, N6 is consequently incremented by 3 Volts: thevoltage at node N2 (now short circuited to node N3) becomes equal to 6volts, the voltage at node N4 (short-circuited to node N5) becomes equalto 9 Volts, and the voltage at node N6 becomes equal to 12 Volts.

As previously discussed, the precharging phase, the charge sharingphase, and the boosting phase are repeatedly performed in succession. Inthis way, the output voltage provided to the load L (i.e., the voltageof the node N6) oscillates among the values of 3 Volts (prechargingphase), 9 Volts (charge-sharing phase) and 12 Volts (boosting phase).The unavoidable draining of electrical charge by the load L from the onestored in the series connection of the capacitors C1, C2 and C3 iscounterbalanced during the boosting phase by the forcing circuit 110,that continuously re-supplies the electrical charge to the seriesconnection of the capacitors.

In practical implementations, the load L is usually connected to thenode N6 of the charge pump 100 by means of a voltage regulator (notshown in the Figure), that allows reducing the voltage swing on the nodeN6, in such a way to obtain an output voltage that is as stable aspossible.

Referring back to the FIGS. 1, 2A, 2B and 2C, the voltage values takenby each node of the charge pump 100 are shown for each one of the threephases.

The detailed structure of the forcing circuits 110 to 160 according to apossible embodiment of the present invention will be now presented.

Referring to FIG. 3A the forcing circuit 110 includes a logic inverter I(e.g., a CMOS inverter) that receives as voltage supplies the supplyvoltage Vdd and the ground voltage GND. The inverter I includes an inputterminal connected to a node L3 which is connected to an output of thelogic block 170, and an output terminal connected to the node N1.

During the precharging and the charge-sharing phases, an input signalprovided by logic block 170 to the inverter I takes a voltage equal to 3Volts, thereby an inverter output signal takes a voltage of 0 Volts(i.e., the ground voltage GND). During the boosting phase, the inputsignal provided by the logic block 170 takes the ground voltage GND.Consequently, the output signal takes a voltage equal to 3 Volts.

It can be appreciated that in this way the node N1 takes the voltagevalues described previously and shown in FIGS. 2A, 2B, and 2C.

Referring to FIG. 3B, the forcing circuit 120 includes a NMOS transistorMB1, having a first terminal connected to a terminal providing theground voltage GND, a gate terminal connected to an output (node L2) ofthe logic block 170 and a second terminal connected to a first terminalof a further NMOS transistor MB2 and forming a circuit node B1. The NMOStransistor MB2 further includes a gate terminal connected to a terminalproviding the supply voltage Vdd, and a second terminal connected to afirst terminal of a PMOS transistor MB3 and forming a circuit node B2.The PMOS transistor MB3 further includes a gate terminal connected to aterminal providing the supply voltage Vdd, a second terminal connectedto the node N2, and a bulk terminal connected to the node N2. Theforcing circuit 120 further includes a PMOS transistor MB4 having afirst terminal connected to the node N2, a second terminal connected toa terminal providing the supply voltage Vdd, a gate terminal connectedto the node B2, and a bulk terminal connected to the node N2. In thefollowing description, and in the remaining of the present description,it is assumed for the sake of simplicity that the threshold values ofboth the NMOS and PMOS transistors are equal to 1 Volt (i.e., +1 voltfor the NMOS transistors, and −1 V for the PMOS transistors); this ishowever not to be intended as a limitation of this embodiment of thepresent invention.

During the precharging phase, the logic block 170 provides a voltageequal to 3 Volts to the gate terminal of the NMOS transistor MB1,activating it, and thus pulling the voltage of the node B1 down to theground voltage GND. Since the voltage of the gate terminal of the NMOStransistor MB2 is equal to 3 Volts, the latter transistor is on, andthus the voltage of the node B2 (and of the gate terminal of the PMOStransistor MB4) is pulled to the ground voltage GND. Consequently, thePMOS transistor MB4 is turned on, and the node N2 takes a voltage equalto 3 Volts, as requested by the correct functioning of the charge pump100. During the precharging phase, the PMOS transistor MB3 is off,because neither its first terminal nor its second terminal take avoltage value higher than 3 Volts.

During the charge-sharing phase, the logic block 170 provides to thegate terminal of the NMOS transistor MB1 the ground voltage GND, thusturning it off. The node B1 remains floating at the ground voltage GND.During the charge sharing phase, the node N2 remains at 3 Volts, andthus the PMOS transistor MB4 remains turned on. The transistors MB2 andMB3 remains in the same state of the previous phase (on and off,respectively).

During the boosting phase, the node N2 takes a voltage value equal to 6Volts, capable of turning the PMOS transistor MB3 on, which in turnprovides the 6 Volts voltage to the node B2. Consequently, the PMOStransistor MB4 is turned off. Meanwhile, the gate terminal of the NMOStransistor MB1 remains at the ground voltage, keeping the transistorturned off. Since even during this phase the NMOS transistor MB2 has itsgate terminal at a voltage equal to 3 Volts, it remains turned on andsets the voltage value of the node B1 to 2 Volts (i.e., the voltage atits gate terminal minus the threshold voltage value).

As can be seen, the voltage values taken by each node of the forcingcircuit 120 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts(i.e., the value of the supply voltage Vdd).

Referring to FIG. 3C, the forcing circuit 130 includes a PMOS transistorMC1, having a first terminal connected to the node N3, a gate terminalconnected to a terminal providing the supply voltage Vdd, a bulkterminal connected to the node N2, and a second terminal connected to afirst terminal of a PMOS transistor MC2, forming a circuit node C1. ThePMOS transistor MC2 further includes a bulk terminal connected to thenode C1, a gate and a second terminals, one connected to each other,forming a circuit node C2. In this way the NMOS transistor MC2 isarranged in a so called diode-configuration. The node C2 is connected toa first terminal and to a bulk terminal of a further PMOS transistorMC3, that further includes a gate and a second terminals, one connectedto each other, and forming a circuit node C3. Even in this case, thePMOS transistor is arranged in a diode-configuration. Similarly, thenode C3 is connected to a first terminal and to a bulk terminal of afurther PMOS transistor MC4, that further includes a gate and a secondterminals, one connected to each other, forming a circuit node C4. Evenin this case, the PMOS transistor is arranged in a diode-configuration.The node C4 is further connected to a first terminal of a PMOStransistor MC6 and to a gate terminal of a NMOS transistor MC7. The PMOStransistor MC6 further includes a gate terminal connected to the nodeN1, a second terminal connected to a terminal providing the supplyvoltage Vdd, and a bulk terminal connected to the second terminal. TheNMOS transistor MC7 further includes a first terminal connected to asecond terminal of a NMOS transistor MC5, forming a circuit node C5, abulk terminal connected to the node C5, and a second terminal connectedto the node N3. The NMOS transistor MC5 further includes a firstterminal connected to a terminal providing the ground voltage GND, and agate terminal connected to an output node (node L2) of the logic block170.

During the precharging phase, the logic block 170 provides a voltageequal to 3 Volts to the gate terminal of the NMOS transistor MC5,activating it; thus, the voltage of the node C5 is pulled to the groundvoltage GND. This implies that the NMOS transistor MC7 is turned on,because its gate voltage is driven to 3 Volts by the PMOS transistorMC6, which has the gate terminal that is at the ground voltage GND, andthe second terminal at a voltage equal to 3 Volts. Consequently to thefact that both the NMOS transistors MC5 and MC7 are turned on, the nodeN3 takes the ground voltage GND, as requested by the correct functioningof the charge pump 100. During the precharging phase, the PMOStransistors MC1, MC2, MC3 and MC4 are turned off, and the nodes C1, C2,C3 are floating. Moreover, the bulk terminal of the PMOS transistor MC1is driven to a voltage value of 3 Volts.

During the charge-sharing phase, the logic block 170 provides to thegate terminal of the NMOS transistor MC5 the ground voltage GND, thusturning it off. Since the PMOS transistor MC6 remains turned on (havingthe second terminal at a voltage of 3 Volts and the gate terminal at theground voltage GND), the gate terminal of the NMOS transistor MC7remains at a voltage of 3 Volts. This implies that the NMOS transistorMC7 remains on, and the node C5 takes a voltage value equal to 2 Volts(the voltage at its gate terminal minus the threshold voltage value).During the sharing phase, the node N3 takes a voltage value of 3 Volts,leaving the PMOS transistor MC1 turned off (its gate terminal has avoltage value equal to 3 Volts). As in the precharging phase, also thePMOS transistors MC2, MC3, MC4 remain turned off, and the nodes C1, C2and C3 are floating.

During the boosting phase, the node N3 takes a voltage value equal to 6volts and the gate terminal of the PMOS transistor MC6 takes a voltagevalue equal to 3 Volts (turning it off), while the logic block 170 stillprovides the ground voltage GND to the gate terminal of the NMOStransistor MC5, and the bulk terminal of the PMOS transistor MC1 isdriven to a voltage value of 6 Volts, capable of turning the PMOStransistor MC1 on, which pulls the voltage of the node C1 to 6 Volts.Consequently, the three diode-configured PMOS transistors MC2, MC3 andMC4 turn on, allowing to provide to the node C4 a voltage value of 3Volts (that can not be provided by the PMOS transistor MC6, that isturned off in this phase). More particularly, each one of the PMOStransistor MC2, MC3 and MC4 acts as a diode having a threshold voltagevalue of 1 Volts, and so the node C2 takes a voltage value of 5 Volts,the node C3 takes a voltage value of 4 Volts, and the node C4 takes avoltage values of 3 Volts.

Even in this case, the voltage values taken by each node of the forcingcircuit 130 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring to FIG. 3D, the forcing circuit 140 includes a NMOS transistorMD1, having a first terminal connected to a terminal providing theground voltage GND, a gate terminal connected to an output node (nodeL2) of the logic block 170, and a second terminal connected to a firstterminal of a further NMOS transistor MD2, forming a circuit node D1.The NMOS transistor MD2 further includes a gate terminal connected to aterminal providing the supply voltage Vdd, and a second terminalconnected to a first terminal of a NMOS transistor MD3, forming acircuit node D2. The NMOS transistor MD3 further includes a gateterminal connected to the node N2, a bulk terminal connected to the nodeD2, and a second terminal connected to a first terminal of a PMOStransistor MD4, forming a circuit node D3. The PMOS transistor MD4further includes a gate terminal connected to the node N2, a secondterminal connected to the node N4, and a bulk terminal connected to thenode N4. The forcing circuit 120 further includes a PMOS transistor MD5having a first terminal connected to the node N4, a second terminalconnected to the node N2, a gate terminal connected to the node D3, anda bulk terminal connected to the node N4.

During the precharging phase, the logic block 170 provides a voltageequal to 3 Volts to the gate terminal of the NMOS transistor MD1,activating it, and thus pulling the voltage of the node D1 to the groundvoltage GND. Since the voltage of the gate terminal of the NMOStransistor MD2 is equal to 3 Volts, the latter transistor is turned on,and thus the voltage of the node D2 is pulled to the ground voltage GNDtoo. Again, thanks to the voltage value of 3 Volts of the node N2, theNMOS transistor MD3 is turned on, and thus the latter transistorprovides the ground voltage GND to the node D3. The ground voltage GNDis in turn provided to the gate terminal of the PMOS transistor MD5,that is turned on. In this way, the node N4 is driven to the voltage ofthe node N2, i.e., 3 Volts. The PMOS transistor MD4 remains turned offduring the precharging phase, because its gate terminal, has a voltagevalue (3 Volts) that it is not lower neither than the one of its firstterminal (0 Volts), nor than the one of its second terminal (3 Volts).

During the charge-sharing phase, the logic block 170 provides to thegate terminal of the NMOS transistor MD1 the ground voltage GND, thusturning it off. The node D1 remains floating at zero voltage. During thecharge-sharing phase, the node N4 takes a voltage value of 6 Volts,while the node N2 remains at a voltage value of 3 Volts. This impliesthat the PMOS transistor MD4 turns on, providing a voltage value of 6Volts to the node D3, in such a way that the PMOS transistor MD5 isturned off. Moreover, the NMOS transistors MD2 and MD3 remain turned on,and the node D2 takes a voltage value of 2 Volts (the voltage at itsgate terminal minus the threshold voltage value).

During the boosting phase, the node N4 takes a voltage value equal to 9Volts, the node N2 takes a voltage value of 6 Volts, while the logicblock 170 continues to provide the ground voltage GND to the gateterminal of the NMOS transistor MD1, that remains turned off. Thanks tothese voltage values, the PMOS transistor MD4 remains on, having thevoltage at the its second terminal higher than the voltage at its gateterminal, keeping the PMOS transistor MD5 turned off. According to thevoltage value of 6 Volts at the node N2, the NMOS transistor MD3 remainson, and the node D2 takes consequently a voltage value of 5 Volts.Moreover, during the boosting phase, the NMOS transistor MD2 remainsturned on too, providing a voltage value of 2 Volts at the node D1.

Even in this case, the voltage values taken by each node of the forcingcircuit 140 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring to FIG. 3E, the forcing circuit 150 includes a PMOS transistorME1, having a first terminal connected to the node N5, a gate terminalconnected to the node N2, a bulk terminal connected to the node N4, anda second terminal connected to a first terminal of a PMOS transistorME2, forming a circuit node E1. The PMOS transistor ME2 further includesa bulk terminal connected to the node E1, and a gate and a secondterminals, one connected to each other, forming a circuit node E2. Inthis way the NMOS transistor ME2 is arranged in a diode-configuration.The node E2 is connected to a first terminal and to a bulk terminal of afurther PMOS transistor ME3, that further includes a gate and a secondterminals, one connected to each other, and forming a circuit node E3.Even in this case, the PMOS transistor is arranged in adiode-configuration. Similarly, the node E3 is connected to a firstterminal and to a bulk terminal of a further PMOS transistor ME4, thatfurther includes a gate and a second terminals, one connected to eachother, forming a circuit node E4. Even in this case, the PMOS transistoris arranged in a diode-configuration. The node E4 is further connectedto a first terminal of a PMOS transistor ME5 and to a gate terminal of aNMOS transistor ME6. The PMOS transistor ME5 further includes a gateterminal connected to the node N3, a second terminal connected to aterminal providing the supply voltage Vdd, and a bulk terminal connectedto the second terminal. The NMOS transistor ME6 further includes a firstterminal connected to a second terminal of a NMOS transistor ME7,forming a circuit node E5, a bulk terminal connected to the node E5, anda second terminal connected to the node N5. The NMOS transistor ME7further includes a first terminal connected to a second terminal of aNMOS transistor ME8, and a gate terminal connected to a terminalproviding the supply voltage Vdd. The NMOS transistor ME8 furtherincludes a gate terminal connected to an output (node L2) of the logicblock 170 and a first terminal connected to a terminal providing theground voltage GND.

During the precharging phase, the logic block 170 provides a voltageequal to 3 Volts to the gate terminal of the NMOS transistor ME8,activating it; thus, the voltage of the node E6 is pulled to the groundvoltage GND. The NMOS transistor ME7 is turned on, because its gatevoltage is equal to 3 Volts, and thus also the voltage of the node E5 ispulled to the ground voltage GND. This implies that the NMOS transistorME6 is turned on, because its gate voltage is driven to 3 Volts by thePMOS transistor ME5, which has the gate terminal at the ground voltageGND, and the second terminal at a voltage equal to 3 Volts. Consequentlyto the fact that the NMOS transistors ME6, ME7 and ME8 are turned on,the node N5 takes the ground voltage GND, as requested by the correctfunctioning of the charge pump 100. During the precharging phase, thePMOS transistors ME1, ME2, ME3 and ME4 are turned off, and the nodes E1,E2, E3 are floating. Moreover, the bulk terminal of the PMOS transistorME1 is driven to a voltage value of 3 Volts.

During the charge-sharing phase, the logic block 170 provides to thegate terminal of the NMOS transistor ME8 the ground voltage GND, thusturning it off. The MOS transistor ME7 remains turned on, providing avoltage of 2 Volts to the node E6. Moreover, the node N3 takes a voltagevalue of 3 Volts, turning off the PMOS transistor ME5, and the node N5takes a voltage value equal to 6 Volts, capable of turning the PMOStransistor ME1 on (the bulk terminal thereof is driven to a voltagevalue of 9 Volts), which pulls the voltage of the node E1 to 6 Volts.Consequently, the three diode-configured PMOS transistors ME2, ME3 andME4 turn on, allowing to provide to the node E4 a voltage value of 3Volts (that can not be provided by the PMOS transistor ME5, that isturned off in this phase). More particularly, each one of the PMOStransistor ME2, ME3 and ME4 acts as a diode having a threshold voltagevalue of 1 Volt, and so the node E2 takes a voltage value of 5 Volts,the node E3 takes a voltage value of 4 Volts, and the node E4 takes avoltage values of 3 Volts. This implies that the NMOS transistor ME6remains on, and the node E5 takes a voltage value equal to 2 Volts (thevoltage at its gate terminal minus the threshold voltage value).

During the boosting phase, the node N5 takes a voltage value equal to 9volts and the gate terminal of the PMOS transistor ME5 takes a voltagevalue equal to 6 Volts (remaining turned off), while the logic block 170still provides the ground voltage GND to the gate terminal of the NMOStransistor ME8, and the bulk terminal of the PMOS transistor ME1 isdriven to a voltage value of 9 Volts. The MOS transistor ME7 remainsturned on, providing again a voltage of 2 Volts to the node E6. Thevoltage of 9 Volts, capable of keeping the PMOS transistor ME1 turnedon, implies that the voltage of the node C1 takes a value of 9 Volts.Consequently, the three diode-configured PMOS transistors MC2, MC3 andMC4 allow to provide to the node E4 a voltage value of 6 Volts (that cannot be provided by the PMOS transistor ME5, that is turned off even inthis phase). More particularly, the node E2 takes a voltage value of 8Volts, the node E3 takes a voltage value of 7 Volts, and the node E4takes a voltage values of 6 Volts. This in turn keeps the NMOStransistor ME6 turned on, with the node E5 that takes a voltage valueequal to 2 Volts.

Even in this case, the voltage values taken by each node of the forcingcircuit 150 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at the limit of 3 Volts,and not beyond.

Referring now to FIG. 3F, the forcing circuit 160 includes a NMOStransistor MF1, having a first terminal connected to a terminalproviding the ground voltage GND, a gate terminal connected to an output(node L2) of the logic block 170, and a second terminal connected to afirst terminal of a further NMOS transistor MF2, forming a circuit nodeF1. The NMOS transistor MF2 further includes a gate terminal connectedto a terminal providing the supply voltage Vdd, and a second terminalconnected to a first terminal of a NMOS transistor MF3, forming acircuit node F2. The NMOS transistor MF3 further includes a gateterminal connected to the node N2, a bulk terminal connected to the nodeF2, and a second terminal connected to a first terminal of a NMOStransistor MF4, forming a circuit node F3. The NMOS transistor MF4further includes a gate terminal connected to the node N4, a bulkterminal connected to the node F3, and a second terminal connected to afirst terminal of a PMOS transistor MF6. The PMOS transistor MF6 furtherincludes a gate terminal connected to the node N4, a second terminalconnected to the node N6, and a bulk terminal connected to the node N6.The forcing circuit 160 further includes a PMOS transistor MF5 having afirst terminal connected to the node N6, a second terminal connected tothe node N4, a gate terminal connected to the node F4, and a bulkterminal connected to the node N6.

During the precharging phase, the logic block 170 provides a voltageequal to 3 Volts to the gate terminal of the NMOS transistor MF1,activating it, and thus pulling the voltage of the node F1 to the groundvoltage GND. Since the voltage of the gate terminal of the NMOStransistor MF2 is equal to 3 Volts, the latter transistor is on, andthus the voltage of the node F2 is pulled to the ground voltage GND too.Again, thanks to the voltage value of 3 Volts of the node N2, the NMOStransistor MF3 is turned on, and thus the latter transistor provides theground voltage GND to the node F3. Being the voltage value of its gateterminal equal to 3 Volts, also the NMOS transistor MF4 is turned on.Consequently, the NMOS transistor MF4 provides the ground voltage GND tothe node F4. The ground voltage GND is in turn provided to the gateterminal of the PMOS transistor MF5, that is turned on. In this way, thenode N6 is driven to the voltage of the node N4, i.e., 3 Volts. The PMOStransistor MF6 remains turned off during the precharging phase, becauseits gate terminal has a voltage value (3 Volts) that it is not lowerneither than the one of its first terminal (0 Volts), nor than the oneof its second terminal (3 Volts).

During the charge-sharing phase, the logic block 170 provides to thegate terminal of the NMOS transistor MF1 the ground voltage GND, thusturning it off. The node F1 remains floating. During the charge-sharingphase, the node N6 takes a voltage value of 9 Volts, while the node N2remains at a voltage value of 3 Volts and the node N4 takes a voltagevalue of 6 Volts. This implies that the PMOS transistor MF6 turns on,providing a voltage value of 9 Volts to the node F4, in such a way thatthe PMOS transistor MF5 is turned off. Moreover, the NMOS transistorsMF2, MF3 and MF4 remain turned on, and the nodes F2 and F3 take voltagevalues of 2 and 5 Volts, respectively.

During the boosting phase, the node N6 takes a voltage value equal to 12Volts, the nodes N2 and N4 take a voltage value of 6 Volts, while thelogic block 170 continues to provide the ground voltage GND to the gateterminal of the NMOS transistor MF1, that remains turned off. Thanks tothese voltage values, the PMOS transistor MF4 remains on, having thevoltage at the its second terminal higher than the voltage at its gateterminal, keeping the PMOS transistor MF5 turned off. According to thevoltage value of 6 Volts at the node N4, the NMOS transistor MF4 remainson, and the node F3 takes consequently a voltage value of 8 Volts.Moreover, the NMOS transistors MF3 and MF2 remain turned on too,providing a voltage value of 2 Volts at the node D1.

Even in this case, the voltage values taken by each node of the forcingcircuit 160 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring back to the FIG. 1, and recalling that the switches S1, S2 areto be controlled in such a way to be open (i.e., not conductive) duringthe precharging phase, and closed (i.e., conductive) during thecharge-sharing and the boosting phases, the logic block 170 is capableto provide to the node L1 (i.e., to the gate terminal of the PMOStransistor of the switch S1) a voltage of 3 Volts during the prechargingphase (node N2 at a voltage of 3 Volts, switch S1 open) a voltage of 3Volts during the boosting phase (node N2 at a voltage of 6 Volts, switchS1 closed), and the ground voltage GND during the charge-sharing phase(node N2 at a voltage of 3 Volts, switch S1 closed). Moreover, since thegate terminal of the PMOS transistor of the switch S2 is connected tothe node N2, it takes a voltage value of 3 Volts during both theprecharging and the charge-sharing phases, and takes a voltage value of6 Volts during the boosting phase. Consequently, in each one of the twoswitches S1 and S2, the voltage differences across its terminals are atthe limit of 3 Volts, and thus the PMOS transistors therein included maybe of the LV transistors type.

According to a further embodiment, the possibility of using so-calledMedium Voltage transistors (hereinafter, MV transistors) iscontemplated. For the purposes of the present description, an MVtransistor is a device designed in such a way to guarantee thecapability of sustaining, at least between a pair of its terminals,voltage differences up-limited by a predetermined maximum voltagedifference ΔVmm higher than the predetermined maximum voltage differenceΔVml that the LV transistors are guaranteed to sustain (i.e., the supplyvoltage Vdd), but still lower than the predetermined maximum voltagedifference ΔVmh guaranteed by HV transistors (for example, assuming thatthe HV transistor can sustain the voltage of the last node N6 of thepump, MV transistors are not designed to sustain such a high voltage).Referring again to the example of circuits including MOS transistors, MVMOS transistors may have gate oxides of thickness capable to avoid oxidebreaking, with voltage differences Vm applied between gate and channelhigher than the supply voltage Vdd, but lower than the voltage outputtedby the charge pump at its last node.

The possibility of including such devices in the forcing circuits of thecharge pump allows to significantly simplify the structure thereof. Moreparticularly, since a MV transistor can sustain voltage differenceshigher than the supply voltage Vdd, the forcing circuits connected tothe nodes of the pump that experience voltages equal or lower than Vm(during all the operating phases of the pump, i.e., during theprecharging, sharing and boosting phases) can be realized in a simplerway. For example, a forcing circuit that make use of MV transistors canbe realized by a single MV transistor, acting as an electronic switch.The single MV transistor may be directly connected between thecorresponding node of the pump and a voltage source providing thevoltage value that is to be imposed on the node during the prechargingphase (the voltage necessary to control the opening/closing of theswitch being for example the voltage of a node of a preceding forcingcircuit). When a node has instead to take a voltage higher than Vm, forexample during the boosting phase, the forcing circuit connected theretoshould have a structure similar to the ones previously described for theexemplary charge pump 100, i.e., including more transistors.

Stabilization and Regulation of the Output Voltage

As previously mentioned, the output voltage provided to the load L(i.e., the voltage of the node N6) oscillates among the values of 3Volts, 9 Volts and 12 Volts. Consequently, since it is desired toprovide an output voltage as stable as possible to the load L, an outputvoltage regulation may be required.

Moreover, the presence of the load L, having in practical cases a finiteequivalent impedance, implies an unavoidable draining of electricalcharge from the one stored in the series connection of the capacitorsC1, C2 and C3. This draining of electrical charge gives rise to anoutput current 11 flowing from the node N6 to the load L (see FIG. 3G).The presence of such load current 11 causes in turn a lowering of thevoltage value outputted by the charge pump. For these reasons, astabilizer capacitor Cs may be included in the structure of the pump100, having a first terminal connected to the node N6 and a secondterminal connected to a terminal providing the ground voltage GND. Thestabilizer capacitor Cs is advantageously implemented in the ICexploiting a depletion region of a semiconductor junction. Thestabilizer capacitor Cs introduces a filtering effect (more precisely, alow-pass filtering effect) in correspondence of the node N6. By properlydimensioning the stabilizer capacitor Cs, i.e., opportunely choosing itscapacitance value, it is possible to limit, or at least slow down, thevariation of the voltage value of the node N6 caused by the drainingeffect due to the presence of the load current II. In fact, with anadequate capacitance value of the stabilizer capacitor Cs, theelectrical charge stored therein may be practically sufficient to supplythe load current II during a cycle of three operating phases of the pump(precharging, charge-sharing, and boosting phase). When the threeoperating phases are performed again, the electrical charge stored inthe stabilizer capacitor Cs is restored by the pump.

As explained in the foregoing, the voltage of the node N6 is ideallycapable to assume only three voltage values (3, 9 and 12 Volts);however, the load L may necessitate voltages different from the onesgenerated by the charge pump. The voltage of each node of the chargepump 100, and in particular of the node N6, is capable of assuming,during the precharging, sharing and boosting phases, a value that isalways a multiple of the voltage that supply the pump, in this exemplarycase the supply voltage Vdd of 3 Volts.

A first solution for obtaining a regulation of the voltage of the nodeN6 consists of modulating the amplitude of the voltage that supply thepump, in such a way to be capable of modulating also the voltage of thenode N6. For this purpose, a first voltage regulator circuit 310 isincluded in the charge pump 100. More particularly, the first voltageregulator circuit 310 is adapted to provide a regulated supply voltageVrs for supplying all the forcing circuits 110-160 by means of a supplyline SL. The supply line SL is connected to the forcing circuits 110-160and to an output terminal of the first voltage regulator circuit 310.The first voltage regulator circuit 310 includes an operationalamplifier 320, having a positive input terminal connected to the supplyline SL, a negative input terminal connected to a reference generatorcircuit 330 providing a reference voltage Vref, and an output terminalconnected to a gate terminal of a PMOS transistor 340. The PMOStransistor 340 further includes a first terminal connected to the supplyline SL and a second terminal connected to a terminal providing thesupply voltage Vdd. The reference generator circuit 330 is connected toa terminal providing the supply voltage Vdd and to a terminal providingthe ground voltage. The reference generator circuit 330 is capable togenerate a reference voltage Vrf having a value ranging from nearly theground voltage GND to nearly the supply voltage Vdd. For example, thereference generator circuit 330 may include a resistive dividercomprising a first resistor R1 and a potentiometer R2. The firstresistor R1 has a first terminal connected to a terminal providing theground voltage GND and a second terminal connected to the negative inputterminal of the operational amplifiers 320. The potentiometer R2 has afirst terminal connected to the second terminal of the resistor R1, asecond terminal connected to a terminal providing the supply voltageVdd, and a ratio terminal connected to the second terminal. The PMOStransistor 340 and the operational amplifier 320 experience at theirterminals voltage differences equal to the supply voltage Vdd or less.Consequently, they can be realized using only LV transistors.

Regulating the potentiometer R2, it is possible to set a desired valuefor the reference voltage Vrf. Thanks to the negative feedback due tothe loop connection of the operational amplifier 320 with the PMOStransistor 340, the value of the regulated supply voltage Vrs tracks thereference voltage Vrf, and is kept stable. In this way, for obtaining adesired voltage value at the node N6, it is necessary to set acorresponding reference voltage Vrf.

Referring to the following table, there are illustrated the voltagevalues of the nodes N1-N6 (during the boosting phase) for threeexemplary different values of reference voltage Vrf. node(s) Vrf = 3Volts Vrf = 2.75 Volts Vrf = 2.5 Volts N6 12 Volts  11 Volts 10 VoltsN5-N4 9 Volts 8.25 Volts 7.5 Volts N3-N2 6 Volts 5.5 Volts 5 Volts N1 3Volts 2.75 Volts 2.5 Volts

A further solution for stabilizing the voltage of the node N6 isillustrated in FIG. 3H. This solution exploits a feedback reactionbetween the supply voltage and the voltage of the node N6, realized bymeans of a second voltage regulator circuit 350.

For this purpose, the supply line SL is connected to the forcingcircuits 110-160 and to an output terminal of the second voltageregulator circuit 350. The second voltage regulator circuit 350 furtherincludes a PMOS transistor 355 having a first terminal connected to thesupply line SL, a second terminal connected to a terminal providing thesupply voltage Vdd, and a gate terminal connected to an output terminalof a comparator 360, that receives as voltage supplies the supplyvoltage Vdd and the ground voltage GND. The comparator 360 furtherincludes a negative input terminal receiving a comparison voltage Vcoand a positive input terminal connected to an output terminal of avoltage divider circuit 365. The voltage divider circuit 365 includes afirst resistor R1′ having a first terminal receiving the ground voltageGND and a second terminal (the output terminal of the voltage dividercircuit 365) connected to the positive input terminal of the comparator360. The voltage divider circuit 365 further includes a second resistorR2′ having a first terminal connected to the second terminal of thefirst resistor R1′. and a second terminal connected to the node N6. Theresistance value of the second resistor R2′ is three times theresistance value of the first resistor R1′. The purpose of the voltagedivider circuit 365 is to provide to the negative input terminal of thecomparator 360 a voltage which value is such to allow an all-LVtransistors implementation of the comparator 360.

More particularly, the resistance values of the first and secondresistors R1′, R′2 are such that the voltage at the positive inputterminal of the comparator 360 results equal to the voltage of the nodeN6 divided by four. Since the higher possible voltage of the node N6 isequal to four times the value of the supply voltage Vdd, dividing it byfour implies having at most a voltage value of 3 Volts, that is, equalto the supply voltage Vdd. In this way, it is possible to implement thecomparator 360 using only LV transistors.

During the charge pump operation, the voltage of the node N6 is firstlydivided by four to obtain a downscaled voltage, and then is comparedwith the comparison voltage Vco. As long as the downscaled voltage islower than the comparison voltage, the comparator 360 keeps the gateterminal of the PMOS transistor 355 to ground, keeping the transistoractivated. In this way, the supply line SL provides a voltage equal tothe supply voltage Vdd to all the forcing circuits 110-160.

Contrarily, if the downscaled exceeds the comparison voltage Vco, thecomparator 360 drives the gate terminal of the PMOS transistor 355 tothe supply voltage Vdd, turning it off. In this way, the supply line SLbecomes floating, and the charge pump tends to turn off. Consequently,the voltage at the node N6 decreases (due to the load draining current),until it falls below the comparison voltage Vcon. At this point, theoutput terminal of the comparator 360 is brought to the ground voltageGND, the PMOS transistor 355 is turned on, and the supply line SL isbrought again to the supply voltage Vdd.

In this way, it is possible regulating the voltage at of the node N6establishing a maximum allowable value thereof. More particularly, sincethe comparator 360 performs a comparison exploiting the voltage of thenode N6 divided by four and the comparison voltage Vco, said maximumallowable voltage is equal to four times the comparison voltage Vco.

Negative Charge Pump

Referring to FIG. 4, a negative serial charge pump 400 according to anembodiment of the present invention is schematically illustrated. Thepurpose of the charge pump 400 is to generate negative voltages lowerthan the IC ground voltage GND. More particularly, the charge pump 400includes a cascade of stages, in the example herein considered threestages. For example, the charge pump 400 is integrated in an IC, such asa semiconductor memory IC, and is adapted to generate a negative voltageused, for example, to erase memory cells. It has to be noted that thecharge pump herein described is an exemplary one, in the sense that thenumber of stages (and thus the number of capacitors) is merelyindicative. Indeed, the teachings of this embodiment of the presentinvention may be referred also to a negative charge pump having adifferent number of capacitors (and thus, having different voltagevalues at the output node).

The generic stage includes a capacitor, like the three capacitors C′1,C′2, C′3. The three capacitors are series connected by means of twoswitches S′′1, S′′2.

The charge pump 400 also includes a plurality of forcing circuits 410,420, 430, 440, 450, 460 adapted to force voltages on a plurality ofnodes N′1, N′2, N′3, N′4, N′5, N′6 of the charge pump in such a way toproperly charge the capacitors C′1, C′2 and C′3, and a logic block 490,adapted to generate control signals whose purpose will be explained inthe following of the description.

More particularly, the capacitor C′1 includes a first plate (incorrespondence of the node N′1) connected to an output terminal of theforcing circuit 410, and a second plate (in correspondence of the nodeN′2) that is connected to a first terminal of the switch S′1. Moreover,the node N′2 is further connected to an output terminal of the forcingcircuit 420.

The switch S′1 includes an NMOS transistor having a first terminalforming the first terminal of the switch, a control terminal (the gateterminal) connected to a first output terminal of the logic block 400(node M1), a bulk terminal connected to the node N′2, and a secondterminal forming the second terminal of the switch S′1, connected to thefirst plate of the capacitor C′2 (in correspondence of the node N′3).Moreover, the node N′3 is connected to an output terminal of the forcingcircuit 430.

The capacitor C′2 has a second plate connected to a first terminal ofthe switch S′2 (in correspondence of the node N′4). The node N′4 isfurther connected to an output node of the forcing circuit 440.

The switch S′2 includes an N-channel MOS transistor having a controlterminal (the gate terminal) connected to the node N′2, a bulk terminalconnected to the node N′4, a first terminal, forming the first terminalof the switch, and a second terminal forming a second terminal of theswitch S′2, connected to a first plate of the capacitor C′3 (incorrespondence of the node N′5). Moreover, the node N′5 is furtherconnected to an output terminal of the forcing circuit 450.

The capacitor C′3 has a second plate connected to an output terminal ofthe forcing circuit 460, in correspondence of the node N′6. The nodeN′6, forming the output node of the charge pump, is further connected toa load, schematized as a bipole L′. For example, the load may be a partof the IC wherein the charge pump is integrated that needs to use thenegative voltage generated by the charge pump.

The logic block 490 further includes a second output terminal connectedto input terminals of the forcing circuits 420, 430, 440, 450 and 460(node M2), a third output terminal connected to an input terminal of theforcing circuit 420 (node M3), a fourth output terminal connected toinput terminals of the forcing circuits 410, 420, 430, 440 and 460 (nodeM4), and a fifth output terminal connected to an input terminal of theforcing circuit 440.

The forcing circuit 440 has a further input terminal connected to thenode N′2; the forcing circuit 450 has two further input terminalsconnected, respectively, to the node M1 and N′2; the forcing circuit 460has four further input terminals connected, respectively, to the nodesN′3, M1, N′2 and N′4.

To better explain the operation of the charge pump 400, reference willbe made now to the FIGS. 5A, 5B and 5C, illustrating simplifiedequivalent circuits of the charge pump 400 during three differentoperating phases: a precharging phase (FIG. 5A), a charge-sharing phase(FIG. 5B), and a voltage boosting phase (FIG. 5C). More particularly, inthe charge pump operation, these three phases are repeatedly performed.

The first, precharging phase serves to charge each one of the capacitorsC′1, C′2 and C′3 to the supply voltage Vdd of the IC (in this exampleequal to 3 Volts). In particular, during this phase, the switches S′1and S′2 are open, and each capacitor C′1, C′2 and C′3 is thus isolatedfrom the other two. The forcing circuits act on the corresponding nodes,so as to bias the first plates of the capacitors to voltages equal tothe supply voltage Vdd, and to bias the second plates of the capacitorsto voltages equal to the ground voltage GND. Consequently, the forcingcircuit 410 biases the node N′1 to the supply voltage Vdd, in theexample of 3 Volts; the forcing circuit 420 biases the node N′2 to theground voltage GND; the forcing circuit 430 biases the node N′3 to avoltage of 3 Volts; the forcing circuit 440 biases the node N′4 to theground voltage GND; the forcing circuit 450 biases the node N5 to avoltage of 3 Volts; and the forcing circuit 460 biases the node N6 tothe ground voltage GND.

After the precharging phase, each capacitor C′1, C′2, C′3 stores anelectrical charge that depends on the respective capacitance value, andon the voltage difference applied across its plates. For example,assuming that all the capacitors C′1, C′2 and C′3 have the samecapacitance value, since in the precharging phase a voltage differenceequal to the supply voltage is applied across the plates of each one ofthe capacitors C′1, C′2, C′3 thanks to the series connection of all thecapacitors guaranteed by the particular topology of the charge pump,each capacitor stores essentially an equal amount of electrical charge.

In the second, charge-sharing operating phase, the switches S′1 and S′2are made to close, so as to connect in series the capacitors C′1, C′2,C′3. Thanks to the series connection, the electrical charge previouslystored in each capacitor C′1, C′2, C′3 is shared with the charge storedin the adjacent capacitor. Moreover, the forcing circuits associatedwith the nodes that modify their voltage values during this phase aredisconnected from the corresponding nodes.

Consequently, the stored electrical charge is redistributed along theseries connection. This involves a change of the voltages present ateach node of the pump 400. More particularly, while the node N′1 remainsat 3 Volts and the node N′2 remains at the ground voltage GND, thevoltage at node N′3 becomes equal to the ground voltage GND, the voltageat node N′4 becomes equal to −3 Volts, the voltage at node N′5 becomesequal to −3 Volts, and the voltage at node N′6 becomes equal to −6Volts.

In the third, boosting phase, the switches S′1 and S′2 remain closed asin the previous phase, and the forcing circuit 410 brings the node N′1from a voltage of 3 Volts to the ground voltage GND. Since all the nodesare connected by means of a capacitive serial connection, the voltage ateach node N′2, N′3, N′4, N′5, N′6 is consequently decremented by 3Volts: the voltage at node N′2 (now short-circuited to the node N′3)becomes equal to −3 Volts, the voltage at node N′4 (short-circuited tothe node N′5) becomes equal to −6 Volts, and the voltage at node N′6becomes equal to −9 Volts.

As previously discussed, the precharging phase, the charge-sharingphase, and the boosting phase are repeatedly performed in succession. Inthis way, the output voltage provided to the load L′ (i.e., the voltageof the node N′6) oscillates among the values of 0 Volts (prechargingphase), −6 Volts (charge-sharing phase) and −9 Volts (boosting phase).The unavoidable draining of electrical charge by the load L′ from theone stored in the series connection of the capacitors C′1, C′2 and C′3is counterbalanced during the boosting phase by the forcing circuit 410,that continuously re-supplies the electrical charge to the seriesconnection of the capacitors.

In practical implementations, the load L′ is usually connected to thenode N′6 of the charge pump 400 by means of a voltage regulator (notshown in the Figure), that allows reducing the voltage swings on thenode N′6, in such a way to obtain an output voltage that is as stable aspossible.

Referring back to the FIGS. 4, 5A, 5B, 5C, the voltage values taken byeach node of the charge pump 400 are shown for each one of the threephases.

The detailed structure of the forcing circuits 410, 420, 430, 440, 450,460 according to a possible embodiment of the present invention will benow presented.

Referring to FIG. 6A, the forcing circuit 410 includes a logic inverterI′ (e.g., a CMOS inverter) that receives as voltage supplies the supplyvoltage Vdd and the ground voltage GND. The inverter I includes an inputterminal connected to an output node (node M4) of the logic block 490,and an output terminal connected to the node N′1.

During the precharging and the charge-sharing phases, an input signalprovided by logic block 490 to the inverter I′ takes a voltage equal tothe ground voltage GND, thereby an inverter output signal takes avoltage value of 3 Volts. During the boosting phase, the input signalprovided by the logic block 490 takes a voltage value equal to 3 Volts.Consequently, the output signal takes the ground voltage GND.

It can be appreciated that in this way the node N′1 takes the voltagevalues described previously and shown in FIGS. 5A, 5B, and 5C.

Referring to FIG. 6B, the forcing circuit 420 includes a NMOS transistorMB′1, having a first terminal connected to the node N′1, a gate terminalconnected to a terminal providing the ground voltage GND, a bulkterminal connected to the node N′2, and a second terminal connected to afirst terminal of a PMOS transistor MB′2, forming a circuit node B′1.The PMOS transistor MB′2 further includes a gate terminal connected to aterminal providing the ground voltage GND, a second terminal connectedto the first terminal of a PMOS transistor MB′3, forming a circuit nodeB′2, and a bulk terminal connected to the node B′2 The PMOS transistorMB′3 further includes a gate terminal connected to the node M2, a secondterminal connected to a terminal providing the supply voltage Vdd, and abulk terminal connected to the second terminal. The forcing circuit 420further includes a NMOS transistor MB′6 having a first terminalconnected to a terminal providing the ground voltage GND, a gateterminal connected to the node M4, a second terminal connected to thenode B2, and a bulk terminal connected to the first terminal. Theforcing circuit 420 still further includes a NMOS transistor MB′5 havinga gate terminal connected to the node B1, a first terminal connected toa second terminal of a NMOS transistor MB′4, forming a circuit node B3,a second terminal connected to the node N′2, and a bulk terminalconnected to the second terminal. The NMOS transistor MB′4 furtherincludes a first terminal connected to a terminal providing the groundvoltage GND, a gate terminal connected to the node M3, and a bulkterminal connected to the first terminal.

During the precharging phase, the logic block 490 provides the groundvoltage GND to the gate terminal of the PMOS transistor MB′3, activatingit, and to the gate terminal of the NMOS transistor MB′6, turning itoff. Consequently, the node B′2 takes a voltage of 3Volts. Since thegate terminal of the PMOS transistor MB′2 is at the ground voltage GND,the latter transistor is turned on, and the node B′1 is brought to avoltage of 3 Volts too. Moreover, the logic block 490 provides a voltageof 3 Volts to the gate terminal of the NMOS transistor MB′4, activatingit. In this way, both the NMOS transistors MB′5 and MB′4 are turned on,and the voltage of the node N′2 is pulled to the ground voltage GND, asrequested by the correct functioning of the charge pump 400. The NMOStransistor MB′1 remains turned off during all the precharging phase.

During the charge-sharing phase, the node N′2 remains at the groundvoltage GND. The logic block 490 provides a voltage of 3 Volts to thegate terminal of the NMOS transistor MB′3, turning it off. Consequently,the node B′1 becomes floating, keeping a voltage of 3 Volts. Moreover,the logic block 490 provides the ground voltage GND to the gateterminals of the NMOS transistors MB′4 and MB′6, turning them off.

During the boosting phase, the node N′2 is brought to a voltage of −3Volts, capable to turn the NMOS transistor MB′1 on (its gate terminal isat the ground voltage GND), pulling the voltage of the node B′1 to −3Volts. The logic block 490 provides a voltage of 3 Volts to the gateterminal of the NMOS transistor MB′6, activating it. Moreover, MB′2 isturned off, because its gate terminal is at the ground voltage GND, itsfirst terminal (node B′1) is at a voltage of 3 Volts, and its secondterminal (node B′2) is pulled to the ground voltage by the NMOStransistor MB′6 The logic block 490 provides a voltage of 3 Volts to thegate terminal of the PMOS transistor MB′3 and the ground voltage GND tothe gate terminal of the NMOS transistor MB′4, keeping the twotransistors turned off during all the boosting phase.

As can be seen, even in this case, the voltage values taken by each nodeof the forcing circuit 420 during each one of the three operating phasesare such to allow the use of LV transistors. In fact, in eachtransistor, the voltage differences across its terminals are at mostequal to 3 Volts.

Referring to FIG. 6C, the forcing circuit 430 includes a PMOS transistorMC′1 having a first terminal connected to the node N′3, a gate terminalconnected to a terminal providing the ground voltage GND, a secondterminal connected to a first terminal of a NMOS transistor MC′2,forming a circuit node C′1, and a bulk terminal connected to the nodeC′1. The NMOS transistor MC′2 further includes a first terminalconnected to a terminal providing the ground voltage GND, a gateterminal connected to the node M4, and a bulk terminal connected to thefirst terminal. The forcing circuit 430 further includes a gate terminalconnected to the node M2, a second terminal connected to a terminalproviding the supply voltage Vdd, and a bulk terminal connected to thesecond terminal.

During the precharging phase, the logic block 490 provides the groundvoltage GND to the gate terminal of the PMOS transistor MC′3 and to thegate terminal of the NMOS transistor MC′2. Consequently, while the NMOStransistor MC′2 is turned off, the PMOS transistor MC′3 is activated,and the node C′1 is brought to a voltage of 3 Volts. in this way, thePMOS transistor MC′1 is on, having the gate terminal at the groundvoltage GND, and the node N′3 is brought to a voltage of 3 Volts, asrequested by the correct functioning of the charge pump 400.

During the charge-sharing phase, the logic block 490 provides a voltageof 3 volts to the gate terminal of the PMOS transistor MC′3, turning itoff, and provides the ground voltage GND to the gate terminal of theNMOS transistor MC′2, keeping it turned off. In this way, the node C′1becomes floating, and takes a voltage of 1 Volt, i.e., the voltage atthe gate terminal of the transistor MC′1 plus the threshold voltage.

During the boosting phase, the node N′3 takes a voltage value equal to−3 Volts, turning off the PMOS transistor MC′1. Meanwhile, the logicblock 490 provides a voltage of 3 Volts to the gate of the transistorMC′2, turning it on. Consequently, the node C′1 is brought to the groundvoltage GND. Moreover, the logic block 490 provides a voltage of 3 Voltsto the gate terminal of the PMOS transistor MC′3, keeping it turned off.

Even in this case, the voltage values taken by each node of the forcingcircuit 430 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring now to FIG. 6D, the forcing circuit 440 includes a NMOStransistor MD′1 having a first terminal connected to the node N′4, agate terminal connected to the node N′2, a second terminal connected tothe gate terminal of a NMOS transistor MD′8, forming a circuit node D′1,and a bulk terminal connected to the node N′4. The NMOS transistor MD′8further includes a first terminal connected to a second terminal of aNMOS transistor MD′7, forming a circuit node D′2, second terminalconnected to the node N′4, and a bulk terminal connected to the secondterminal. The NMOS transistor MD′7 further includes a first terminalconnected to the node N′2, a gate terminal connected to the node M5, anda bulk terminal connected to the node N′4. The forcing circuit 440further includes a PMOS transistor MD′2 having a first terminalconnected to the node D′1, a gate terminal connected to the node N′2, asecond terminal connected to a first terminal of a PMOS transistor MD′3,forming a circuit node D′3, and a bulk terminal connected to the nodeD′3. The PMOS transistor MD′3 further includes a gate terminal connectedto a terminal providing the ground voltage GND, a second terminalconnected to a first terminal of a PMOS transistor MD′4, forming acircuit node D′4, and a bulk terminal connected to the node D′4. ThePMOS transistor MD′4 further includes a gate terminal connected to thenode M2, a second terminal connected to a terminal providing the supplyvoltage Vdd, and a bulk terminal connected to the second terminal. Theforcing circuit 440 further includes a NMOS transistor MD′6 having afirst terminal connected to the node N′2, a gate terminal connected tothe node M1, a second terminal connected to the node D′3, and a bulkterminal connected to the node N′2. Moreover, a further NMOS transistorMD′5 is included, having a first terminal connected to a terminalproviding the ground voltage, a gate terminal connected to the node M4,a second terminal connected to the node D′4 and a bulk terminalconnected to the first terminal.

During the precharging phase, the node N′4 is pulled to the groundvoltage GND by turning on the NMOS transistors MD′8 and MD′7. For thispurpose, the logic block 490 provides a voltage of 3 Volts to the gateof the NMOS transistor MD′7, that has the first terminal at the groundvoltage GND, and the node D′1 is driven to a voltage of 3 Volts by meansof the activation of the PMOS transistors MD′2, MD′3 and MD′4. Moreparticularly, the logic block 490 provides the ground voltage GND to thegate terminal of the PMOS transistor MD′4, turning it on. Consequently,the node D′4 takes a voltage of 3 Volts. In this way, the PMOStransistor MD′3 is turned on, because its gate terminal is at the groundvoltage, and also the node D′3 takes a voltage of 3 Volts. Since in theprecharging phase the node N′2 is brought to the ground voltage GND, andsince the PMOS transistor MD′2 has the gate terminal connected to thenode N′2, the latter transistor turns on, providing a voltage of 3 Voltsto the node D′1. The transistors MD′1, MD′5 and MD′6 remain turned offduring all the precharging phase.

During the charge-sharing phase, the node N′4 takes a voltage valueequal to −3 Volts, turning on the NMOS transistor MD′1, which has thegate terminal at the ground voltage GND. In this way, the node D′1 takesthe voltage value of the node N′4, (−3Volts), turning off the PMOStransistor MD′2. The logic block 490 provides a voltage of 3 Volts tothe gat terminal of the NMOS transistor MD′6, turning it on. In thisway, the node D′3 is brought to the ground voltage GND, turning off thePMOS transistor MD′3. Moreover, the PMOS transistor MD′4 is turned offby the logic block 490, that provides a voltage of 3 Volts to its gateterminal. Since the node D′1 is at a voltage of−3 Volts, the NMOStransistor MD′8 is turned off. Moreover, the logic block 490 provides avoltage of 3 Volts to the NMOS transistor MD′7, keeping it turned on.Furthermore, the NMOS transistor MD′5 is kept turned off during all thecharge-sharing phase, being its gate terminal at the ground voltage GND.

During the boosting phase, the node N′4 is brought to a voltage equal to6 Volts. The NMOS transistor MD′1 remains turned on (its gate terminalis brought to a voltage of −3 Volts). Consequently, the node D′1 takes avoltage value of 6 Volts, keeping the NMOS transistor MD′8 turned off.In fact, its first terminal is brought to −3 Volts by the NMOStransistor MD′7, activated in turn by the logic block 490, that providesthe ground voltage GND to the gate terminal of the latter transistor.Moreover, the PMOS transistor MD′2 remains turned off, because its gateterminal, connected to the node N′2, is at a voltage of −3 Volts, whilethe node D′3 is brought to a voltage of −3 Volts by the NMOS transistorMD′6. In fact, the logic block 490 provides the ground voltage GND tothe gate terminal of the latter transistor, having the first terminal ata voltage of −3 Volts during all the boosting phase. Being the node D′3at a voltage of −3Volts, the PMOS transistor MD′3 remains turned off.Moreover, the logic block 409 provides a voltage of 3 Volts to the gateterminal of the NMOS transistor MD′5, that in turn pulls the node D′4 tothe ground voltage GND. The PMOS transistor MD′4 remains turned off alsoduring the boosting phase.

Even in this case, the voltage values taken by each node of the forcingcircuit 440 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring to FIG. 6E, the forcing circuit 450 includes a PMOS transistorME′1 having a first terminal connected to the node N′5, a gate terminalconnected to the node N′2, a second terminal connected to a firstterminal of a PMOS transistor ME′3, forming a circuit node E′1, and abulk terminal connected to the node E′1. The PMOS transistor ME′3further includes a gate terminal connected to the node M1, a secondterminal connected to a first terminal of a PMOS transistor ME′5,forming a circuit node E′2, and a bulk terminal connected to the nodeE′2. The PMOS transistor ME′5 further includes a gat terminal connectedto the node M2, a second terminal connected to a terminal providing thesupply voltage Vdd, and a bulk terminal connected to the secondterminal. The forcing circuit 450 further includes a NMOS transistorME′2 having a first terminal connected to the node N′2, a gate terminalconnected to the node M1, a second terminal connected to the node E′1,and a bulk terminal connected to the first terminal. Moreover, theforcing circuit 450 still further includes a NMOS transistor ME′4 havinga first terminal connected to a terminal providing the ground voltageGND, a gate terminal connected to the node M2, a second terminalconnected to the node E′2, and a bulk terminal connected to the firstterminal.

During the precharging phase, the logic block 490 provides the groundvoltage GND to the gate terminals of the PMOS transistors ME′5, ME′3 andME′1. Consequently, while the NMOS transistor ME′4 is turned off (itsgate terminal is driven by the logic block 490 in such a way to take theground voltage GND), the PMOS transistor ME′5 is activated, and the nodeE′2 is brought to a voltage of 3 Volts. In this way, the PMOS transistorME′3 is activated, having the gate terminal at the ground voltage GND,and the node E′1 is brought to a voltage of 3 Volts. As a consequence,the PMOS transistor is turned on, and the node N′5 is brought to avoltage of 3 Volts, as requested by the correct functioning of thecharge pump 400. The logic block 490 provides the ground voltage to thegate terminal of the NMOS transistor ME′2, that, having the firstterminal at the ground voltage too, remains turned off during all theprecharging phase.

During the charge-sharing phase, the node N′5 takes a voltage valueequal to −3 Volts. This voltage value is such to turn off the PMOStransistor ME′1, which has the gate terminal at the ground voltage GND.The NMOS transistor ME′2 is turned on, because, while its first terminalis brought to the ground voltage GND, the logic block 490 provides toits gate terminal a voltage of 3 Volts. Consequently, the node E′1 takesthe ground voltage GND, turning off the PMOS transistor ME′3 (its gateterminal is driven by the logic block 490 to a voltage of 3 Volts).Moreover, the node E′2 is brought to the ground voltage GND by the NMOStransistor ME′4, that is turned on by the logic block 490 (its gateterminal is brought to a voltage of 3 Volts). The PMOS transistor ME′5,having the gate terminal at a voltage of 3 Volts, remains turned offduring all the charge-sharing phase.

During the boosting phase, the node N′5 takes a voltage value of −6Volts. The logic block 490 provides a voltage of −3 Volts to the gateterminal of the PMOS transistor ME′1, keeping it turned off. The NMOStransistor ME′2 is kept turned on (its gate terminal is driven to theground voltage GND, and its first terminal is at a voltage of −3 Volts),driving thus the voltage of the node E′1 to the voltage of the node N′2,i.e. to −3 Volts. Moreover, the node E′2 is kept at the ground voltageGND by the NMOS transistor ME′4, which has its gate terminal at avoltage of 3 Volts, and the PMOS transistors ME′3 and ME′5 are keptturned off. In fact, the logic block 490 provides the ground voltage GNDto the gate terminal of the PMOS transistor ME′3, and a voltage of 3Volts to the gate terminal of the PMOS transistor ME′5.

Even in this case, the voltage values taken by each node of the forcingcircuit 450 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring to FIG. 6F, the forcing circuit 460 includes a NMOS transistorMF′1 having a first terminal connected to the node N′6, a gate terminalconnected to the node N′4, a second terminal connected to the gateterminal of a NMOS transistor MF′8, forming a circuit node F′1, and abulk terminal connected to the node N′6. The NMOS transistor MF′8further includes a first terminal connected to a second terminal of aNMOS transistor MF′7, forming a circuit node F′2, a second terminalconnected to the node N′6, and a bulk terminal connected to the secondterminal. The NMOS transistor MF′7 further includes a first terminalconnected to the node N′4, a gate terminal connected to the node N′3,and a bulk terminal connected to the node N′6. The forcing circuit 460further includes a PMOS transistor MF′2 having a first terminalconnected to the node F′1, a gate terminal connected to the node N′4, asecond terminal connected to a first terminal of a PMOS transistorMF′10, forming a circuit node F′5, and a bulk terminal connected to thenode F′5. The PMOS transistor MF′10 further includes a gate terminalconnected to the node N′2, a second terminal connected to a firstterminal of a PMOS transistor MF′3, forming a circuit node F′3, and abulk terminal connected to the node F′3. The PMOS transistor MF′3further includes a gate terminal connected to a terminal providing theground voltage GND, a second terminal connected to a first terminal of aPMOS transistor MF′4, forming a circuit node F′4, and a bulk terminalconnected to the node F′4. The PMOS transistor MF′4 further includes agate terminal connected to the node M2, a second terminal connected to aterminal providing the supply voltage Vdd, and a bulk terminal connectedto the second terminal. The forcing circuit 460 further includes a NMOStransistor MF′9 having a first terminal connected to the node N′4, agate terminal connected to the node N′2, a second terminal connected tothe node F′5, and a bulk terminal connected to the first terminal.Moreover, the forcing circuit 460 still further includes a NMOStransistor MF′6 having a first terminal connected to the node N′2, agate terminal connected to the node M1, a second terminal connected tothe node F′3, and a bulk terminal connected to the node N′2.Furthermore, the forcing circuit 460 includes a NMOS transistor MF′5,having a first terminal connected to a terminal providing the groundvoltage, a gate terminal connected to the node M4, and a second terminalconnected to the node F′4.

During the precharging phase, the node N′6 is pulled to the groundvoltage GND by turning on the NMOS transistors MF′8 and MF′7. For thispurpose, the logic block 490 provides a voltage of 3 Volts to the gateof the NMOS transistor MD′7, that has the first terminal at the groundvoltage GND, and the node F′1 is driven to a voltage of 3 Volts by meansof the activation of the PMOS transistors MF′2, MF′10, MF′3 and MF′4.More particularly, the logic block 490 provides the ground voltage GNDto the gate terminal of the PMOS transistor MF′4, turning it on.Consequently, the node F′4 takes a voltage of 3 Volts. In this way, thePMOS transistor MF′3 is turned on, because its gate terminal is at theground voltage, and also the node F′3 takes a voltage of 3 Volts. Sincein the precharging phase the node N′2 is brought to the ground voltageGND, and since the PMOS transistor MF′10 has the gate terminal connectedto the node N′2, the latter transistor turns on, providing a voltage of3 Volts to the node F′5. In the same way, since in the precharging phasethe node N′4 is brought to the ground voltage GND, and since the PMOStransistor MF′2 has the gate terminal connected to the node N′4, thelatter transistor turns on, providing a voltage of 3 Volts to the nodeF′1. The transistors MF′1, MF′9, MF′5 and MF′6 remain turned off duringall the precharging phase.

During the charge-sharing phase, the node N′6 takes a voltage valueequal to −6 Volts, turning on the NMOS transistor MF′1, which has thegate terminal at a voltage of −3 Volts. In this way, the node F′1 takesthe voltage value of the node N′6, (−6Volts), turning off the PMOStransistor MF′2 (its gate terminal is at a voltage of −3 Volts). Thelogic block 490 provides the ground voltage GND to the gate terminal ofthe NMOS transistor MF′9, turning it on. In this way, the node F′5 isbrought to a voltage of −3 Volts. The logic block 490 provides a voltageof 3 Volts to the gate terminal of the NMOS transistor MF′6, turning iton (its first terminal is at the ground voltage GND). In this way, thenode F′3 is brought to the ground voltage GND. Since its gate terminalis kept at the ground voltage GND, the PMOS transistor MF′10 is turnedoff. Moreover, the PMOS transistor MF′4 is turned off by the logic block490, that provides a voltage of 3 Volts to its gate terminal.Consequently, the node F′4 becomes floating. The PMOS transistor MF′3,having the gate terminal at the ground voltage GND, is turned off. Sincethe node F′1 is at a voltage of −6 Volts, the NMOS transistor MD′8 isturned off. Moreover, the logic block 490 provides the ground voltageGND to the gate terminal of the NMOS transistor MD′7, keeping it turnedon, being its first terminal at a voltage of −3 Volts. Furthermore, theNMOS transistor MF′5 is kept turned off during all the charge-sharingphase, being its gate terminal at the ground voltage GND.

During the boosting phase, the node N′6 takes a voltage value of −9Volts. The NMOS transistor MF′1 remains turned on (its gate terminal isbrought to a voltage of −6 Volts). Consequently, the node F′1 takes avoltage value of −9 Volts, keeping the NMOS transistor MF′8 turned off.In fact, its first terminal is brought to −6 Volts by the NMOStransistor MF′7, having in turn the gate terminal at a voltage of −3Volts and the first terminal at a voltage of −6 Volts. Moreover, thePMOS transistor MF′2 remains turned off, because its gate terminal,connected to the node N′4, is at a voltage of −6 Volts, while the nodeF′5 is brought to a voltage of −6 Volts by the NMOS transistor MF′9(having the gate terminal at a voltage of −3 Volts and the firstterminal at a voltage of −6 Volts). Moreover, the node F′3 is brought toa voltage of −3 Volts by the NMOS transistor MF′6. In fact, the logicblock 490 provides the ground voltage GND to the gate terminal of thelatter transistor, having the first terminal at a voltage of −3 Voltsduring all the boosting phase. Being the node D′3 at a voltage of−3Volts, the PMOS transistors MF′3 and MF′10 remains turned off.Moreover, the logic block 490 provides a voltage of 3 Volts to the gateterminal of the NMOS transistor MF′5, that in turn pulls the node F′4 tothe ground voltage GND. The PMOS transistor MF′4 remains turned off alsoduring the boosting phase.

Even in this case, the voltage values taken by each node of the forcingcircuit 460 during each one of the three operating phases are such toallow the use of LV transistors. In fact, in each transistor, thevoltage differences across its terminals are at most equal to 3 Volts.

Referring back to the FIG. 4, and recalling that the switches S′1, S′2are to be controlled in such a way to be open (i.e., not conductive)during the precharging phase, and closed (i.e., conductive) during thecharge-sharing and the boosting phases, the logic block 490 is capableto provide to the gate terminal of the NMOS transistor of the switch S′1(node M1) the ground voltage GND during the precharging phase (node N′2at the ground voltage GND, S′1 open), a voltage of 3 Volts during thecharge-sharing phase (node N′2 at the ground voltage GND, S′1 closed),and the ground voltage GND during the boosting phase (node N′2 at avoltage of −3 Volts, S′1 closed). Moreover, since the gate terminal ofthe NMOS transistor of the switch S′2 is connected to the node N′2, ittakes a the ground voltage GND during both the precharging and thecharge-sharing phases, and takes a voltage equal to −3 Volts during theboosting phase. Consequently, in each one of the two switches S1 and S2,the voltage differences across its terminals are at the limit of 3Volts, and thus the NMOS transistors therein included may be of the LVtransistors type.

The exemplary circuital structures described herein allow to realizeboth positive and negative charge pumps avoiding the necessity of usingHV circuit components. In particular, the adoption of the serial chargepump architecture intrinsically allows avoiding the use of HVcapacitors, because every capacitor is subjected to a voltage differenceat most equal to the supply voltage Vdd. Moreover, the innovativebiasing of the various forcing circuits allows avoiding the use of HVtransistors. This in turn allows reducing the silicon area occupied bythe ICs including high voltage circuits, and to simplify theirmanufacturing.

Charge pumps formed according to embodiments of the present inventioncan be utilized in a variety of different types of integrated circuits,such as memory devices. Moreover, such integrated circuits can becontained in a variety of different types of electronic systems such ascomputer systems and handheld devices like cellular phones, and personaldigital assistants (PDAs).

Naturally, in order to satisfy local and specific requirements, a personskilled in the art may apply to the solution described above manymodifications and alterations. Particularly, although the presentinvention has been described with a certain degree of particularity withreference to preferred embodiment(s) thereof, it should be understoodthat various omissions, substitutions and changes in the form anddetails as well as other embodiments are possible; moreover, it isexpressly intended that specific elements and/or method steps describedin connection with any disclosed embodiment of the invention may beincorporated in any other embodiment as a general matter of designchoice.

1. A charge pump circuit comprising at least one pump stage, said pumpstage including: a capacitor having a first plate and a second plate; afirst circuital node connected to the first plate, a voltage of thefirst circuital node being forced to a first forced voltage during aforcing phase of the charge pump operation; a second circuital nodeconnected to the second plate, a voltage of the second circuital nodebeing forced to a second forced voltage during the forcing phase, thevoltages of the first and the second circuital nodes being free ofchanging with respect to the first and to the second forced voltages,respectively, except during said forcing phase,; a first forcing circuitassociated to the first circuital node, the first forcing circuit beingactivable for forcing the voltage of the first circuital node to thefirst forced voltage during the forcing phase; and a second forcingcircuit associated to the second circuital node, the second forcingcircuit being activable for forcing the voltage of the second circuitalnode to the second forced voltage during the forcing phase, wherein thefirst and second forcing circuits comprise each at least one electronicdevice having terminals, wherein: said at least one electronic device isdesigned to guarantee the capability of sustaining voltage differencesacross the terminals thereof that are up-limited in absolute value by apredetermined maximum voltage equal to a multiple of the absolute valueof the difference between the first and the second forcing voltages andlower than an absolute value of a charge pump output voltage; and thefirst and second forcing circuits include means for ensuring that thevoltage difference applied across pair of terminals of said at least oneelectronic device is not higher than the predetermined maximum voltagewhen at least one among the voltages of the first and the secondcircuital nodes change to a voltage higher in absolute value than saidpredetermined maximum voltage.
 2. The charge pump circuit of claim 1,wherein at least one among said first and second forcing circuitscomprises: a switch inserted between the respective circuital node and aforcing voltage supplier terminal, the switch including a controlterminal, a first terminal connected to the respective circuital nodeand a second terminal connected to the forcing voltage supplierterminal; a switch activation circuit connected to the control terminalof the switch, adapted to activate the switch during the forcing phasein such a way to transfer the first, respectively second forced voltageto the first, respectively second circuital node; and a bootstrapcircuit coupled to the respective circuital node and the controlterminal of the switch, the bootstrap circuit being connected betweenthe first, respectively second circuital node and the control terminalof the switch and being adapted to ensure that a voltage differenceacross the control, the first and the second terminals of the switch andbetween the switch control terminal and the switch activation circuitwhen the voltage of the first, respectively second circuital nodechanges with respect to the first, respectively second forced voltage isnot higher in absolute value than the predetermined maximum voltage. 3.The charge pump of claim 2, wherein the bootstrap circuit of the firstforcing circuit includes first coupling means for coupling the voltageof the first circuital node to the control terminal of the switch, andthe bootstrap circuit of the second forcing circuit includes secondcoupling means for coupling the voltage of the second circuital node tothe control terminal of the switch.
 4. The charge pump of claim 3,wherein the first coupling means includes at least one first controlledvoltage transfer mean having a control terminal adapted to be driven byvoltages higher than the higher between the first and second forcingvoltages or lower than the lower between the first and second referenceforcing voltages for ensuring that a voltage difference between thecontrol terminal of the at least one first controlled voltage transfermean, the first circuital node, and the switch control terminal is nothigher in absolute value than the predetermined maximum voltage.
 5. Thecharge pump of claim 2, wherein both the first and the second forcingcircuits comprise the switch, the switch activation circuit, and thebootstrap circuit.
 6. The charge pump of claim 5, wherein the secondcoupling means include at least one second controlled voltage transfermean having a control terminal adapted to be driven by voltages higherthan the higher between the first and second forcing voltage forensuring that a voltage difference between the control terminal of theat least one second controlled voltage transfer mean, the secondcircuital node, and the switch control terminal is not higher inabsolute value than the predetermined maximum voltage.
 7. The chargepump of claim 6, wherein the at least one among the first and secondforcing circuits includes a voltage supplier circuit, coupled to theforcing voltage supplier terminal, capable to provide the first or,respectively, the second forced voltage for forcing the first,respectively second circuital node.
 8. The charge pump of claim 7,wherein the voltage supplier circuit of the first forcing circuit iscapable to interrupt the supply of the first forced voltage to the firstcircuital node during at least a phase different from the forcing phase;and the bootstrap circuit of the second forcing circuit is capable todeactivate the switch during at least a phase different from the forcingphase.
 9. The chare pump of claim 2, wherein: the first forcing circuitcomprises the switch, the switch activation circuit, and the bootstrapcircuit; and the second forcing circuit is capable to interrupt thesupply of the second forced voltage to the second circuital node duringat least a phase different from the forcing phase.
 10. The charge pumpof claim 9, wherein the first forcing circuit includes a voltagesupplier circuit coupled to the forcing voltage supplier terminal,capable to provide the first forced voltage for forcing the firstcircuital node, said voltage supplier circuit being capable to interruptthe supply of the first forced voltage to the first circuital nodeduring at least a phase different from the forcing phase.
 11. The chargepump of claim 1, wherein said at least one pump stage includes at leasta first and a second pump stages cascade connected by means of switchingmeans, the second circuital node of the first pump stage being connectedto the first circuital node of the second boost stage by means of theswitching means.
 12. The charge pump of claim 1, further including: anoutput node for providing the charge pump output voltage, the outputnode being a first or a second circuital node of a pump stage; and afirst regulating circuit connected to the forcing voltage supplierterminal adapted to set the charge pump output voltage to a desiredregulated voltage by regulating the voltage of the forcing voltagesupplier terminal.
 13. The charge pump of claim 1, further including: anoutput node for providing an output boosted voltage, the output nodebeing a first or a second circuital node of a pump stage; and a secondregulating voltage connected between the forcing voltage supplierterminal and the output node adapted to regulate the charge pump outputvoltage by selectively interrupting the providing of the voltage of theforcing voltage supplier terminal basing on a comparison between thecharge pump output voltage and a reference voltage.
 14. The charge pumpof claim 1, wherein the first and second forcing circuits includes onlyelectronic devices designed to guarantee the capability of sustainingvoltage differences across terminals thereof that are up-limited inabsolute value by a predetermined maximum voltage equal to the absolutevalue of the difference between the first and the second forcingvoltages and lower than a charge pump output voltage.
 15. The chargepump of claim 1, wherein said multiple is equal to one.
 16. The chargepump of claim 1, wherein: said multiple includes a first multiple and asecond multiple lower than the first multiple; the predetermined maximumvoltage includes a first predetermined maximum voltage equal to thefirst multiple of the absolute value of the difference between the firstand the second forcing voltages and a second predetermined maximumvoltage equal to the second multiple of the absolute value of thedifference between the first and the second forcing voltages; and the atleast one electronic device is selected from the group consisting of afirst electronic device and a second electronic device, the firstelectronic device being designed to guarantee the capability ofsustaining voltage differences across terminals thereof that areup-limited in absolute value by the first predetermined maximum voltageand lower than a charge pump output voltage and the second electronicdevice being designed to guarantee the capability of sustaining voltagedifferences across terminals thereof that are up-limited in absolutevalue by the second predetermined maximum voltage and lower than acharge pump output voltage.
 17. A method of operating a charge pumpcircuit comprising at least one charge pump stage including: a capacitorhaving a first plate and a second plate; a first circuital nodeconnected to the first plate; a second circuital node connected to thesecond plate; a first forcing circuit associated with the firstcircuital nodes for forcing the voltage of the first circuital nodeexploiting at least one electronic device having terminals; and a secondforcing circuit associated with the second circuital nodes for forcingthe voltage of the second circuital node exploiting at least oneelectronic device; the method including the steps of: forcing thevoltage of the first circuital node to a first forced voltage during aforcing phase of the charge pump operation; and forcing the voltage ofthe second circuital node to a second forcing voltage during the forcingphase, wherein said steps of forcing the voltage include: ensuring thatthe voltage difference applied across the terminals of said at least oneelectronic device is not higher than a predetermined maximum voltageequal to a multiple of the absolute value of the difference between thefirst and the second forcing voltages and lower than an absolute valueof a charge pump output voltage when at least one among the voltages ofthe first and the second circuital nodes change to a voltage higher inabsolute value than said predetermined maximum voltage.
 18. A chargepump comprising at least one pump stage circuit and a forcing circuitcoupled to each pump stage circuit, each pump stage circuit including aplurality of electronic components and the forcing circuit being adaptedto receive first and second forcing voltages, the forcing circuitoperable to control voltages applied to the electronic components ofeach pump stage circuit to develop a charge pump output voltage on anoutput of the pump stage circuit, the forcing circuit being furtheroperable to limit voltages across the electronic components of each pumpstage circuit to a maximum voltage having a magnitude equal to amultiple of the difference between the first and the second forcingvoltages, the maximum voltage being less than a magnitude of the chargepump output voltage and the forcing circuit being further operable tolimit voltages across each electronic component to the maximum voltageresponsive to a voltage having a magnitude that is greater than themaximum voltage being applied to the component.
 19. The charge pump ofclaim 18 wherein the first forcing voltage comprises a supply voltagethe second forcing voltage comprises a ground reference voltage.
 20. Thecharge pump of claim 18 wherein the electronic components compriseswitches.
 21. The charge pump of claim 20 wherein the switches compriselow-voltage MOS transistors.
 22. The charge pump of claim 18 wherein thecharge pump output voltage comprises a negative output voltage.
 23. Anintegrated circuit, comprising: electronic circuitry including a chargepump, the charge pump comprising at least one pump stage circuit and aforcing circuit coupled to each pump stage circuit, each pump stagecircuit including a plurality of electronic components and the forcingcircuit being adapted to receive first and second forcing voltages, theforcing circuit operable to control voltages applied to the electroniccomponents of each pump stage circuit to develop a charge pump outputvoltage on an output of the pump stage circuit, the forcing circuitbeing further operable to limit voltages across the electroniccomponents of each pump stage circuit to a maximum voltage having amagnitude equal to a multiple of the difference between the first andthe second forcing voltages, the maximum voltage being less than amagnitude of the charge pump output voltage and the forcing circuitbeing further operable to limit voltages across each electroniccomponent to the maximum voltage responsive to a voltage having amagnitude that is greater than the maximum voltage being applied to thecomponent.
 24. The integrated circuit of claim 23 wherein the electroniccircuitry includes memory circuitry.
 25. The integrated circuit of claim24 wherein the memory circuitry includes non-volatile memory cells. 26.An electronic system, comprising: electronic circuitry including anintegrated circuit, the integrated circuit containing a charge pumpcomprising at least one pump stage circuit and a forcing circuit coupledto each pump stage circuit, each pump stage circuit including aplurality of electronic components and the forcing circuit being adaptedto receive first and second forcing voltages, the forcing circuitoperable to control voltages applied to the electronic components ofeach pump stage circuit to develop a charge pump output voltage on anoutput of the pump stage circuit, the forcing circuit being furtheroperable to limit voltages across the electronic components of each pumpstage circuit to a maximum voltage having a magnitude equal to amultiple of the difference between the first and the second forcingvoltages, the maximum voltage being less than a magnitude of the chargepump output voltage and the forcing circuit being further operable tolimit voltages across each electronic component to the maximum voltageresponsive to a voltage having a magnitude that is greater than themaximum voltage being applied to the component.
 27. The electronicsystem of claim 26 wherein the electronic circuitry comprises a computersystem.
 28. A method of controlling a charge pump circuit to provide acharge pump output voltage, the charge pump circuit including at leastone pump stage circuit including a plurality of electronic components,the method comprising: developing control voltages to control theoperation of each pump stage circuit, the control voltages being derivedfrom first and second forcing voltages; limiting voltages across theelectronic components of each pump stage circuit to a maximum voltagehaving a magnitude equal to a multiple of the difference between thefirst and the second forcing voltages, the maximum voltage being lessthan a magnitude of the charge pump output voltage; and limitingvoltages across each electronic component to the maximum when a voltagehaving a magnitude that is greater than the maximum voltage would beapplied to the component.
 29. The method of claim 28 wherein the chargepump output voltage comprises a negative output voltage.
 30. The methodof claim 28 wherein the first forcing voltage comprises a positivesupply voltage and the second forcing voltage comprises a negativesupply voltage.